Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains, which are chains of flip-flops that are used to form serial shift registers for applying test patterns at inputs to combinational logic of the integrated circuit and for reading out the corresponding results.
As integrated circuits have become increasingly complex, scan compression techniques have been developed which reduce the number of test patterns that need to be applied when testing a given integrated circuit, and therefore also reduce the required test time. However, the use of high levels of scan compression can adversely impact diagnostic resolution, that is, the ability to attribute a particular failure to an exact fault or set of faults within the combinational logic. As a result, when using scan compression, a tradeoff exists between compression level and diagnostic resolution. Additional details regarding compressed scan testing are disclosed in U.S. Pat. No. 7,831,876, entitled “Testing a Circuit with Compressed Scan Subsets,” which is commonly assigned herewith and incorporated by reference herein.
It is also well known to provide an integrated circuit with built-in self-test (BIST) functionality so as to allow that integrated circuit to test its internal combinational logic without the need for an external test system. For example, integrated circuits comprising embedded memories are often configured to include memory BIST (MBIST) circuitry for testing the operation of the memory cells within a memory array.
A significant problem with existing techniques for MBIST testing of embedded memory in an integrated circuit is that there is typically certain sequential logic or other functional logic at the input or output of the memory that is not covered by the MBIST testing. For example, during MBIST testing the functional address and data paths going into the embedded memory are usually bypassed and an MBIST controller instead provides the address and data inputs for the memory array being tested, which unfortunately provides no test coverage for the functional address and data paths. It should be noted that this problem is not limited to integrated circuits that include embedded memory and utilize MBIST. Similar test coverage problems can arise in other types of integrated circuits.